As the degree of integration of semiconductor devices increase, there has been interest in methods for reducing the size of all components and elements integrated on a semiconductor substrate. One particular area of interest is in optimizing a technology for reducing a shallow trench isolation region, which occupies considerable area on a semiconductor device.
The device isolation region may be formed by a local oxidation of silicon (LOCOS) method or a shallow trench isolation method (STI).
In the LOCOS method, a nitride layer and an oxide mask defining an active region is formed. A predetermined region of a substrate is oxidized to form a device isolation region. The oxidation process progresses not only vertically within the substrate, but also horizontally, which causes an undesirable region of oxide geometrically isomorphic to a bird's beak. This horizontal spreading of the isolation region decreases the usable area of the active region.
In the STI method, a trench is formed in a predetermined region of a semiconductor substrate and is filled with an oxide material to a great thickness. A chemical mechanical polishing (CMP) then completes the device isolation region. However, when the oxide material is deposited, the thickness of the oxide layer varies between the edge region of the semiconductor substrate and the central region. The oxide layer in the central region is thicker than that in the edge region.
Accordingly, if the polishing is performed to planarize the edge region, an unplanarized oxide layer remains in the central region. Conversely, if the polishing is performed to planarize the central region, a moat is formed in the trench in the edge region.
Ideally, when a device isolation region is formed in a semiconductor substrate, the oxide layer in the central region is completely removed without forming a moat in the trenches in the edge region.